/*
 * Copyright (c) Huawei Technologies Co., Ltd. 2023-2024. All rights reserved.
 * Description: vRoCE common context.
 * Create: 2023-8-9
 */

#ifndef VROCE_CONTEXT_FORMAT_H
#define VROCE_CONTEXT_FORMAT_H

#define VROCE_ACL_IP_VALUE_WIDTH         9
#define VROCE_ACL_IP_KEY_LEN   20
#define VROCE_ACL_IP_KEY_LEN_16  16
#define VROCE_ACL_IP_VALUE_LEN   36
#define IP_ENTRY_KEY_LEN         VROCE_ACL_IP_KEY_LEN
#define IP_ENTRY_VALUE_LEN       VROCE_ACL_IP_VALUE_LEN
#define VROCE_MIG_CACHE_LINE_NUM 8

#define VROCE_MIG_ENTRY_KEY_LEN     20
#define VROCE_MIG_ENTRY_VALUE_LEN   40

enum {
    VROCE_CMD_TIME_CLASS_A = 3000,
    VROCE_CMD_TIME_CLASS_B = 4000,
    VROCE_CMD_TIME_CLASS_C = 5000
};

#define VROCE_MAX_GID_NUM_PER_PORT       (128)
#define VROCE_GID_TABLE_SIZE             (32)
#define VROCE_GID_DWORD_LEN              (VROCE_GID_TABLE_SIZE >> 2)
#define VROCE_XID_MASK                   (0xfffff)

typedef struct roce_gid_entry {
    u8 gid_info[VROCE_GID_TABLE_SIZE];
} roce_gid_entry_s;

typedef struct {
    union {
        struct {
#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN))
            u32 rsvd : 9;
            u32 valid : 1;
            u32 cl_size : 2;
            u32 cl_end : 10;
            u32 cl_start : 10;
#else
            u32 cl_start : 10;
            u32 cl_end : 10;
            u32 cl_size : 2;
            u32 valid : 1;
            u32 rsvd : 9;
#endif
        } bs;
        u32 value;
    };
} vroce_mig_cache_line_s;

#endif /* VROCE_CONTEXT_FORMAT_H */